VerilogWeb
Fill in the architecture to build a functional ALU for RV32I. The operands are 32 bits each.
The operation should be performed according the 4-bit input operation, which is made up of {imm7[5], imm3} from the instruction.
This is summarized in the following table (note that these are listed in order shown on the instruction reference, not in binary order):
| 0000 | ADD | (add) |
| 1000 | SUB | (subtract) |
| 0001 | SLL | (shift left logical) |
| 0010 | SLT | (set if less than) |
| 0011 | SLTU | (set if less than unsigned) |
| 0100 | XOR | (bitwise XOR) |
| 0101 | SRL | (shift right logical) |
| 1101 | SRA | (shift right arithmetic) |
| 0110 | OR | (bitwise OR) |
| 0111 | AND | (bitwise AND) |
module alu(input logic[31:0] operand1,
input logic[31:0] operand2,
input logic[3:0] operation,
output logic[31:0] result);
// You're building a real processor!!
endmodule
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